A Macroscale Simulator for Exascale Software/Hardware Co-Design

The next decade will see a rapid evolution of HPC node architectures as power and cooling constraints are limiting increases in microprocessor clock speeds and constraining data movement. Future and current HPC applications will have to change and adapt as node architectures evolve. The application of advanced exascale architecture simulators will play a crucial role for the design and optimization of future data intensive applications. In this paper, we present our imulation-based framework for analyzing the scalability and performance of massive interconnected networks. *Corresponding author: Damian Dechev, Department of Electrical Engineering and Computer Science, University of Central Florida, Orlando, FL, USA, E-mail: [email protected] Received August 10, 2013; Accepted November 18, 2013; Published November 23, 2013 Citation: Dechev D, Hendry G (2013) A Macroscale Simulator for Exascale Software/Hardware Co-Design. J Inform Tech Softw Eng 3: 123. doi:10.4172/21657866.1000123 Copyright: © 2013 Dechev D, et al. This is an open-access article distributed under the terms of the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are credited.